It is commonplace in electronic art, particularly the semiconductor art to use multiple layers of conductors to interconnect different devices or device regions. For example, power and ground may be distributed on one layer of interconnections while signals are distributed on a different layer or, all the interconnections on a first layer may be aligned in a first direction while the interconnections on a second layer are aligned in a second direction at right angles to the first direction. Other arrangements are also used. Multiple conductor layers permit more compact device and circuit layouts. This is highly desirable.
The various conductors, conductor layers, or interconnections are typically of metal although semiconductors and other conductive materials are also employed. As used herein the word "interconnections, interconnects, metal, metallization, conductor, conductive, or conducting" whether used singly or in combination with the prefix "multi-" or the words "multi-layer" are intended to refer to any conductive material, including, but not limited to metals, semiconductors, semimetals, and intermetallics.
Multi-layer metal arrangements and methods are known in the semiconductor art. The multiple metal layers are separated by one or more dielectric insulating layers except at particular points where conductive vias are provided. It is important that the surfaces of the successive conductor and dielectric layers be as smooth and free from cracks and steps as possible, since such features produce weak points in the overlying layers which adversely affect yield and reliability. Sometimes, the via is merely an opening in the intervening dielectric layer through which the upper metal layer penetrates so that it locally contacts the lower metal layer. In this circumstance the upper metal layer may have to pass over a sharp step at the edge of the via hole. In order to avoid such sharp steps, via holes in the prior art have frequently been outwardly tapered. But, outwardly tapered vias occupy greater surface area and are therefore undesirable for use in VLSI and other very dense or compact structures.
It is preferable to use an approximately straight-sided via hole through the inter-layer dielectric which is filled with a conductive pillar or column whose upper surface joins as smoothly as possible with the upper surface of the dielectric layer and whose sides are approximately vertical. This minimizes the surface discontinuities and surface area. As used herein, the words "pillar" or "column" are intended to be equivalent, and to refer to a conductive region passing between superimposed conductor layers through a via hole having sidewalls which are approximately vertical or which slope inwardly.
A process for forming conductive columns or pillars is described in copending application Ser. No. 717,343 by Hulseweh, entitled "Pillar Via Process", which is incorporated herein by reference. This and other processes for forming such conductive pillars are sensitive to the surface area of the pillar and the surface area of other exposed conductors which must be simultaneously formed. If, for example, the process is adjusted to make the surface of a first pillar (having a first area) locally flush with the surface of the dielectric interlayer, so that the two surfaces smoothly join without a crack or step, then other exposed pillars or conductors having different areas will not be flush and smoothly joined with the dielectric surface but will lie above or below the dielectric surface by different amounts creating a step and/or crack. This is due to the fact that the planarizing action of the dielectric inter-layer is area dependent. This area dependence can create or exaggerate surface steps. The problem is particularly severe when large area exposed conductors, such as bonding pads, and small area exposed pillars must be provided in the same conductor layer.
Accordingly, it is an object of the present invention to provide an improved process for forming conductive pillars or vias in electronic devices, for example, between multiple conductor layers in semiconductor integrated circuits.
It is a further object of the present invention to provide an improved process for forming conductive pillars or vias and exposed contact regions of different areas in the same device.
It is an additional object of the present invention to provide an improved process for forming relatively small area conductive pillars or vias, and relatively large area exposed bonding pads in the same conductor layer.
It is a further object of the present invention to provide an improved process for forming conductive pillars or vias and exposed contact regions of different areas, without an increase in pillar or via area, and without requiring outwardly tapered via holes.
It is an additional object of the present invention to provide an improved process for forming conductive pillars or vias without requiring the use of additional photomasking layers on the device.